SIEMENS EDA SEMINAR
Design, Model and Validate 3D IC Systems
Join us to master 3D package design and predictive system validation in this hands-on, multi-domain engineering workshop.
Wednesday, April 8, 2026
About the workshop
To sustain the rapid scaling of AI performance, the semiconductor industry is increasingly turning to heterogeneous integration and 2.5D/3D IC architectures. But as dies stack closer together, electrical, thermal, and mechanical interactions become tightly coupled, making overall system performance and reliability far more difficult to predict and validate.
How can engineers ensure these disciplines work together effectively to design reliable 3D IC systems?
Join Siemens and Oregon State University for an in-person technical workshop exploring a system-centric approach to 3D IC design. Through practical examples and engineering workflows, this event will demonstrate how early package planning, calibrated thermal modeling, and system-level simulation can help reduce design risk and accelerate development cycles.
Event Details
Date: Wednesday, April 8, 2026
Time: 10:00 AM – 4:00 PM
Location: Oregon State University – Corvallis, OR
- Johnson Hall 105 SW 26th Street, Corvallis, OR 97331
- Room 221 - Academic Success Classroom
Cost: Complimentary (Lunch Included)
What You’ll Learn
- How early 3D package planning impacts downstream thermal and reliability performance
- Methods for gaining thermal visibility during electrical design
- Thermal transient testing fundamentals and structure function calibration
- Secure compact modeling (BCI-ROM) for transient and multi-die simulation
- Multi-scale cooling strategies from package to board to system
- Engineering tradeoff exploration using physics-driven workflows
Who Should Attend
- Package and substrate designers
- Thermal and mechanical engineers
- System architects
- Power and RF engineers
- Researchers and graduate students in semiconductor disciplines
This workshop offers an opportunity to:
- Engage directly with Siemens EDA and simulation experts
- Connect with regional semiconductor professionals
- Explore practical approaches to reducing design risk
- Strengthen collaboration between academia and industry
If you have questions, please contact Shawn Baggerley