User2User Europe - Usability Lab
The User2User Usability Lab provides attendees the opportunity to test the latest EDA products to provide valuable feedback and ask questions about our tools. Lab participants will receive a free gift while supplies last.
Aprisa™
Aprisa™ Auto Macro Placement
Explore Aprisa's AI-driven Auto Macro Placement (AMP) feature by generating an effective expert-designer quality floorplan, in a very short amount of time. Then dive deeper into AMP’s interactive capabilities such as smart repack, which empowers designers to fine-tune the macro placement and achieve optimal Quality of Results (QoR).
Calibre®
Calibre® RealTime: Creating a Complex Recipe Using the Calibre RealTime Recipe Editor
Try the Calibre® RealTime Check Recipe Editor, one of the most powerful capabilities to create custom recipes. Use the Recipe Editor to create more complex recipes with “intersect” operators.
Insight Analyzer
With a focus on finding transistor leakage and floating gates very early in the design process, this lab steps you through the easy-to-use interface to create a project, run built-in checks, and explore the results showing real circuit issues. Insight EDA was recently acquired by Siemens and is part of the Calibre family, complementing Calibre® PERC™ reliability flows much earlier in the custom digital and analog design flows.
Calibre® Pattern Matching: Find Pattern
Find any pattern in a design at the push of a button. Users will quickly flag all matching locations in Calibre® nmDRV with this interactive solution.
Calibre® Pattern Matching: IP Checker
The IP Checker helps secure internal and third-party IPs from misuse by guaranteeing that after placement, routing, and fill, the placed IP stays true to the original version. The IP Checker identifies matching placements and flags any differences between the placed IP and the original version in case of modifications
Cloud Flow
Project Cloud Flow: Burst Heavy Compute Batch Workloads into the Cloud from a Local Machine
Project Cloud Flow allows you to securely and seamlessly burst EDA workloads into the cloud without changing your workflow or tools, and without the need for in-house Cloud expertise. In this lab, you can launch Calibre® nmDRC physical verification or Analog FastSPICE™ platform simulations from a local machine into the cloud with the same ease as submitting to a local HPC grid.
Catapult® & PowerPro®
Catapult®: High-Level Synthesis Design Exploration, Power Estimation, and Optimization
Experience the process of synthesizing, simulating, and performing power estimation and optimization for a standard polyphase decimating filter with different operating frequencies and system level performance tradeoffs. See how fundamental memory architecture and area/delay tradeoffs can impact the PPA of silicon from the same untimed C++ source.
PowerPro®: Reducing RTL Power Using Guided Optimization
See how PowerPro power optimization reduces design power at each stage of RTL. Perform power linting with PowerPro’s static, functional and micro-architecture checks. Find out which hierarchies exhibit glitches that can impact your design power. Perform fine-grained sequential clock gating and memory gating to get significantly power optimized, energy efficient RTL.
DVT/ Questa®
Questa® Developer Active Analysis & Design Creation
A common design scenario occurs during a new project creation when IP cores from a previous project are to be used. Before adding the cores to the new project, the previous cores must be checked for adherence to the latest coding standards. This lab illustrates how the advanced features of Questa Developer can assist and guide users to fix compilation and coding issues. The design understanding-related features provided by Questa Developer can also assist a new team’s comprehension of an IP’s structure. After fixing any basic coding issues, the lab is completed by running a simulation testbench with the cores to show the tight integration between design management in Questa Developer and simulation in QuestaSim. This lab is intended for RTL design engineers, verification engineers and managers of design and design verification teams.
Verify Secure
Try the Verify Secure app, an automated tool for verifying the data path security of hardware designs. Verify Secure ensures that data and instructions flow securely through the hardware, preventing unauthorized parties from gaining access to sensitive information or disrupting the system's operation. In this lab, you will practice path definitions for verifying secure path and non-secure path, learn how to set up and run Verify Secure, and learn GUI basics for investigating existing paths.
Tessent™
Tessent™ Visualizer: Explore Tessent Visualizer
Explore the variety of features in the Tessent Visualizer GUI. Understand your design, analyze object connectivity with advanced tracer features, and see how this tool can simplify your DFT tasks.
Tessent™ Visualizer: Wave Viewer
Experience an interactive session on debugging IJTAG (E14 DRC) with our recently released Wave Viewer functionality. Explore the Test Setup visualization feature and find the root cause of X mismatches in the test procedure.
Tessent™ Visualizer: Single Data Rate Clocking for SSN
Learn how to configure Tessent Streaming Scan Network (SSN) to use single data rate (SDR) clocking. Use the Config Data Browser to review the configuration and explore the configured network using other visualization features.